Design a High-Resolution ECG with a Fully Differential Amplifier and High-Resolution ADC

Contributed By Digi-Key's North American Editors

Typical medical noninvasive ECGs create basic visual representations of the heart’s state of health for clinical analysis and medical intervention. However, there are some details of heart operation, such as “late potential”, that require extremely high-resolution ECG electronics. The spatial resolution required for these images can be compromised by noise and other performance inhibitors at the electrocardiogram (ECG) detector, the detector system, and even by the acquisition technique.

Designers can avoid many problems and develop a high-precision ECG system by effectively applying a low-noise driver and a high-resolution analog-to-digital converter (ADC).

This article briefly discusses how ECGs work before detailing the issues associated with pairing a driver amplifier with a high-resolution ADC for this application. It then introduces a sample combination comprising the Analog Devices ADA4945-1ACPZ-R7 high-speed, fully differential ADC driver and the Analog Devices eight-channel, 24-bit AD7768BSTZ ADC, and shows how to configure external resistors and capacitors to achieve optimal performance.

The ECG system

The ECG is a noninvasive test that reflects underlying heart conditions by collecting heart generated millivolt (mV) electrical signals. The ECG signals can be detected at many points on the body, but decades of medical tradition have standardized the accepted locations of those points in an imaginary formation of three limb leads, called Einthoven’s triangle (Figure 1).

Diagram of ECG signals can be detected at many points on the bodyFigure 1: ECG signals can be detected at many points on the body, but Einthoven’s triangle defines the generally accepted locations. (Image source: Digi-Key Electronics)

The triangle describes the placement of electrodes RA (right arm), LA (left arm), and LL (left leg). They also form VI, VII, and VIII values.

The data from this system allows doctors to understand the underlying rate and rhythm mechanism of the heart. However, with further examination the data can provide evidence of increased thickness (hypertrophy) and damage to the various parts of the heart muscle. Additionally, the simple two-dimensional ECG graph can provide evidence of acutely impaired blood flow to the heart muscle or patterns of abnormal electric activity that may predispose the patient to abnormal cardiac rhythm disturbances.

The normal heart’s ECG signal is shown, emphasizing the normal combination of three of the graphical deflections seen on a typical electrocardiogram, called the QRS complex (Figure 2).

Diagram of Q, R, and S points create the QRS complexFigure 2: The Q, R, and S points create the QRS complex, usually the central and most visually obvious part of an ECG tracing. (Image source: Digi-Key Electronics)

The QRS complex is the central and obvious part of the signal. This signal corresponds to the depolarization of the right and left ventricles of the human heart. In adults, the QRS complex normally lasts 0.08 to 0.10 seconds (s). A QRS complex duration of greater than 0.12 s is considered abnormal. The measurement challenge in the ECG system is to reliably and completely capture the QRS signal.

This challenge isn’t too difficult. Theoretically, the sample rate for ECG equipment is at least 50 Hz. Real ECG implementations have sampling frequency of more than 500 Hz, with the typical conversion speed of the ECG detector’s internal converter ≥1 kilohertz (kHz). With these sample rates, the required resolution of typical ECG detection system internal converters is 12 bits.

These resolution and speed specifications are consistent with a general purpose ECG detector. However, some heart irregularities can only be detected with higher resolution ECG detectors. For example, patients that present sustained ventricular tachycardia (VT) may have low amplitude, high frequency waveforms in the terminal QRS complex that persist for tens of milliseconds. These “late potentials” in ECG results are thought to be caused by early afterdepolarizations of cells in the right ventricle (Figure 3).

Graph of ECG results occur during the QRS complexFigure 3: Late potentials in the ECG results occur during the QRS complex but are often too small to show up on typical ECG detectors. (Image source: Digi-Key Electronics)

The late potential amplitudes are often too small to show up on a normal ECG. However, with high-resolution systems greater than 20 bits, the ADC averages the QRS complex recordings internally to filter out random noise, so late potentials become visible in the ECG image.

There are significant clinical implications when non-invasive, high-resolution ECGs can detect cardiac late potentials. For example, with patients that have acute myocardial infarction (MI), late potential detection is prognostically significant. The ventricular late potential’s presence in such patients is an indicator of risk from subsequent MI or sudden cardiac death. Earlier this classification and subsequent diagnosis was possible only by way of invasive or minimally invasive techniques.

However, to make the originally undetectable signals visible using an ECG, advanced signal acquisition and processing techniques using high-resolution sigma-delta (ƩΔ) ADCs is required.

High-resolution conversion systems

A typical ECG system has twelve electrodes that affix to the patient’s skin, sensing the millivolt—divided by 1,000, or microvolt (mV)—heart signals. Each of these electrode signals arrives at the signal conditioning front-end where the instrumentation amplifiers gain the microvolt signal in preparation for the driver amplifier and ultimately the high-resolution, ƩΔ ADC (Figure 4).

Diagram of ECG front-end signal conditioning block diagramFigure 4: An ECG front-end signal conditioning block diagram for a high-resolution medical sensing system, starting with three op amp instrumentation amplifiers. (Image source: Digi-Key Electronics)

The first devices in the signal chain are three precision op amp instrumentation amplifiers and possibly a second gain stage. These devices establish system ground and differential gain for the low microvolt level signals. The driver amplifier and low-pass filter (LPF) acquire the differential gained ECG signal providing ample drive and filtering for the high-resolution ƩΔ ADC.

Driver amplifier and ƩΔ-ADC

A critical function in the front-end signal conditioning block diagram is the driver amplifier and ƩΔ ADC relationship. An ADA4945-1 fully differential ADC driver stimulates the input to the high-resolution AD7768-4 ƩΔ ADC (Figure 5).

Image of typical connection diagram for the high-resolution ƩΔ ADC Analog Devices AD7768-4Figure 5: Typical connection diagram for the high-resolution ƩΔ ADC AD7768-4, with the ADA4945-1 as a driver amplifier. (Image source: Digi-Key Electronics, based on source material from Analog Devices)

The ADA4945-1 driver amplifier and the R/C, LPF network send the signal to the input of the ƩΔ ADC (AD7768-4).

The AD7768-4 is a four-channel, 24-bit, simultaneous sampling ƩΔ ADC. The AD7768-4 is reconfigured with selectable power modes and digital filter options to suit a wide range of applications, including ECGs, industrial input/output modules, instrumentation, audio testing, control loops, and condition monitoring.

Measuring performance

The ADA4945-1 has two fully characterized full-power and low-power modes, optimizing trade-offs between system power and performance. The full-power bandwidth of the ADA4945-1 is 145 megahertz (MHz), while in the low-power mode the bandwidth is 80 MHz. With a 5 volt power supply, the input voltage noise at 100 kHz in the full-power mode is 1.8 nV/√Hz versus 3 nV/√Hz in the low-power mode. Finally, the operating quiescent current of the ADA4945-1 in full-power mode is 4 milliamps (mA) (typ) and 4.2 mA (max). In low-power mode it is 1.4 mA (typ) and 1.6 mA (max).

The AD7768-4 low-power mode offers a 32 kilosamples per second (kSPS) output data rate (ODR) and 12.8 kHz of bandwidth when using the wideband digital filter. The 1 kHz input applied sine wave signal is −0.5 decibels (dB) from full scale. Median power mode has 128 kSPS ODR with 51.2 kHz of bandwidth when using the wideband filter. The 1 kHz input applied sine wave signal is −0.5 dB from full scale. Fast power mode provides 256 kSPS ODR with 102.4 kHz of bandwidth when using the wideband filter. Table 2 (below) shows the performance and power consumption for the ADA4945-1 and AD7768-4 power combinations.

The AD7768-4 configured filter response has a 0.433 × ODR cutoff frequency. A ±0.005 dB pass-band ripple allows frequency domain measurements to determine drive amplifiers vs. input frequency performance.

In Figure 5, there is a resistor-capacitor (R/C) network between the amplifier output and the ADC input. The R/C network performs a variety of tasks. For example, C1 and C2 are charge reservoirs to the ADC and provide the ADC with fast charge current to the sampling capacitors.

In addition, these capacitors in combination with the RIN resistor, form a low-pass filter to remove glitches related to the input switching. The input resistance also stabilizes the amplifier when driving large capacitive loads and prevents the amplifier from oscillating (Table 1).

Amplifier Mode ADC Mode RIN (Ω) C1, C2 (pF) FC (MHz) Supply Voltage (V)
Low Power Low Power 82 82 23.7 0 and 5
Low Power Median Power 82 120 16.2 0 and 5
Fast Power Full Power 82 470 4.1 0 and 5

Table 1: Appropriate values for RIN, C1 and C2. (Data source: Analog Devices)

With the system in Figure 5, this evaluation fixture produces a signal-to-noise ratio (SNR) of 106.7 dB and a total harmonic distortion (THD) of −114.8 dB with a subsystem power level as low as 18.45 milliwatts (mW) (Table 2).

Amplifier Mode ADC Mode Power (mW) SNR (dB) THD (dB) SINAD (dB)
Low Power Low Power 18.45 106.7 -114.8 106.2
Low Power Median Power 18.80 106.7 -117.7 106.3
Fast Power Full Power 30.5 105.9 -116.6 105.6

Table 2: Performance comparison using a mix of two ADA4945-1 amplifier modes and three AD7768-4 ADC modes. (Data source: Analog Devices)

The SNR of the op amp/ADC combination shows that the system resolution is:

            Resolution = (SNR – 1.76)/6.02

                                 = 17.43 bits

This high-resolution driver ADC amplifier and Σ-Δ ADC combination produces an accurate output and completely eliminates the need for post-processing.

To evaluate the hardware, designers can use the EVAL-AD7768-4FMCZ evaluation board with the AD7768-4 and an amplifier mezzanine card (AMC) carrying the ADA4945-1 (Figure 6).

Image of Analog Devices EVAL-AD7768-4FMCZ evaluation board for the AD7768-4Figure 6: The EVAL-AD7768-4FMCZ evaluation board for the AD7768-4 can be used to test the design by adding an AMC populated by the ADA4945-1. (Image source: Analog Devices with ADA4945-1 callout added by Digi-Key Electronics for clarity)

This evaluation platform can be configured to use an AMC-ADA4500-2ARMZ mezzanine card for ADC drivers, with one channel only, as the driver amplifier input. The EVAL-SDP-CH1Z high-speed design evaluation board is connected to the EVAL-AD7768-4FMCZ evaluation platform to use the supplied evaluation software. A precision audio source is used for AC analysis.


High-resolution ECGs can non-invasively detect heart anomalies that would either go unnoticed or have indicators that would require invasive or minimally invasive detection procedures. However, the resolution required for these ECGs can be compromised by noise and other performance inhibitors at the ECG detector, the detector system, and even the acquisition technique.

As shown, designers can avoid many problems and develop a high-precision, high-resolution ECG by effectively combining the Analog Devices ADA4945-1ACPZ-R7 high-speed, fully differential ADC driver and the Analog Devices eight-channel, 24-bit AD7768BSTZ ADC. The combination also creates buffer/digital filtering circuits that eliminate the need for post-processing equipment.

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