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Timing-Slide4

Shown on this slide is a typical two socket Xeon-based server. The diagram is the same whether Sandybridge or Ivybridge CPUs are used. This is the first server to support PCIe Gen3. Critical performance characteristics, in addition to phase jitter, are skew between the BCLKs (CPU clocks) and the PCIe Clocks into the CPUs, and also skew between the sets of these clocks going to each CPU. That is why Intel recommends that all of these clocks be sourced from a single clock chip, hence the Z buffer specification.

PTM Published on: 2012-06-28