Concerto™ is based on a 65 nm F021 Flash technology. The M3 master system and the C28x control system operate from independent Flash banks. The M3 Flash is 512 kB that split into fourteen distinct sectors. As with the ROM, it cannot be accessed from the µDMA. Flash technology used in the F28M35x device has an overall cycle time of 25 ns or 40 MHz. This number includes any ECC error detection and correction overhead and any overhead associated with performance acceleration mechanisms, and caching. To boost code execution performance, acceleration hardware is added which consists of 128-bit wide, two level, pre-fetched mechanism. After the first 128-bit wide fetch, the Flash interface will fetch ahead the next 128-bit wide word, while the currently fetched instructions are fed to the CPU. In theory, a 128-bit wide word can hold four 32-bit instructions or eight 16-bit instructions. Hence, the system can provide near single-cycle performance even if the Flash wait states are as high as three or four cycle access. In addition to instruction pre-fetch mechanisms, the M3 master system Flash interface also implements 128-bit instruction cache. Simulations have shown that this can significantly boost performance for certain algorithms without severely impacting the predictability of the execution, which can be critical in real-time systems. An eight byte data cache is also supported in the device. During the Flash memory operation, a write page erase or a mass erase access to the Flash memory is prohibited. Since the 28x and the M3 share the same pump, there is a Flash semaphore for pump ownership.