Settings
Fast Delivery
Free Shipping
Incoterms
Payment Types
Marketplace Product
Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Product List
This slide shows the host side RAM of the device. Concerto™ has 96 kB of RAM split into twelve distinct blocks of 8 kB each. Two additional 2 kB blocks are reserved for inter processor communication. M2C is for the M3 to control side exchange and C2M is for the C28x core to M3 exchange, C-blocks are dedicated to the M3 side; S blocks are shared. Initially TI will have all the eight shared RAM blocks matched to the M3 side. For control need, four by eight or 32kB might be needed. It is possible to remap S0, S2, S4, and S6 to the C28 side. Moving forward, if more is required, even the whole shared RAM, all of the blocks can be allocated to the DSP.
PTM Published on: 2012-08-01
Ireland