To increase interrupt service, speed, and efficiency, TI uses what is called a tail chaining model. In this, the processor state is automatically stored to the stack on an exception and is automatically restored from the stack at the end of the interrupt service routine. The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Furthermore, it is not only the priority of the interrupt, but how the interrupts are handled. This shows how it takes fewer cycles for the Cortex to handle different interims. Reduced cycles was a target enhancement from the existing ARM7 architectures. As a reminder, an ARM7 thumb architecture, which would serve interrupts as follows: twenty six cycles from IRQ1 to ISR1, which is up to forty two cycles within the LSM mode; forty two cycles from ISR1 exit to ISR2 entry; or sixteen cycles to return from ISR2. This equates to approximately a 65% cycle overhead saving versus the existing ARM7 cores.