The Concerto™ devices also feature the EPI, or the external peripheral interface. This is a high speed parallel bus for external peripherals or memory. It is similar to a standard microprocessor address or data bus. It does have several modes of operation to interface gluelessly to many types of external devices. Please note though that the right FIFO buffer allows FIFOed writes to separate the processor from timing details. SDRAM is supported by sixteen single data rates up to 50 MHz or about 64 mB. It includes automatic refresh and access to all banks and rows and includes sleep and standby modes to keep contents alive with minimal power draw. This also supports host bus interface, with the traditional by eight and by sixteen MCU interface capabilities which allow access to SRAM, NOR, Flash, and other similar devices. In the host bus mode, interface mode, addresses and data can be demuxed allowing 1 MB addressing or multiplex to address up to 256 MB. Whatever the constraints of the external memory may be, the EPI can easily be configured to communicate with it through flexible settings such as the read/write, write speed for speed control. Device compatibility options, similar to what is on the PIC18, Mega, 8051 cores and a host of other devices, access a range of devices supporting the non-addressed FIFO by eight interface variances, which supports for transmit empty and receive full for FIFO empty and FIFO full flags. There is also a manual chip enable for the use of extra address pins. The EPI also supports machine-to-machine mode through a wide parallel interface for fast communications which is up to about 150 MB per second with the CPLDs and FPGAs with a configurable address width and the range from four to six bits. Optional clock outputs, read/write strobes, framing, counter-based size, and clock enabled inputs are also supported in machine-to-machine mode. The customer can also use this as a general parallel GPIO. This mode supports communication with a parallel type of peripheral. Actuators traditionally use GPIO and certain data acquisition systems are based on it. GPIO ranges from one to 32-bit width through the FIFO buffer. Using the EPI offers the host flexibility to control speed to fit virtually any external device constraints. The EPI must be connected to just one type of external device at a time. Switching from one type of device to another on the fly is possible, but it would require the user to reconfigure the EPI. This could lead to a malfunctioning if, for instance, the EPI is switched from SDRAM mode to Flash. Since SDRAM will then not be refreshed, its contents may be lost. Therefore, enhanced capabilities include µDMA support, clocking control, and support for external FIFO buffers. The EPI controller provides predictable operation and thus has an advantage over regular GPIO which has more variable timing due to on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction completes, non-blocking reads are performed in the background and allow the processor to continue operation.