Shown on this slide is the Cortex™-M3 core architecture that is included in the Concerto™ device. The Concerto host subsystem is based on the Cortex-M3, a 32-bit machine, which features the Harvard architecture characterized by separate busses for instruction and data. Interrupts are fully C-programmable and there is no need for assembly boot code or assembly system configuration. ARM7 compilers, on the other hand, normally come with an assembly boot routine in object form that performs the setup. In the Concerto device, the Cortex-M3 hardware loads the stack pointer from memory and the initial PC from memory and enters as a normal C function. The use of C and C++ code is all that is required for programming. Cortex-M3 supports 32-bit words, 16-bit half words, and 8-bit bytes. Processor also supports 64-bit data transfer instructions and all instructions and data memory accesses are Little-endian. Cortex-M3 processor integrates hardware support for interrupts through its nested interrupt controller, which will be referred to as the NVIC later on, to deliver high interrupt performance. The memory protection unit, referred to as the MPU, improves system reliability. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault causing a fault exception and possibly causing termination of the process in a OS environment. The M3 core also comes with an enhanced system debug with extensive breakpoint and trace capabilities. However, please note that serial wire debug is not supported by the Concerto device. Concerto devices include additional write protection to critical registers, and this is achieved by using a double write method. In this method, there is a write allow register or WRALLOW register, which if written with a particular value will allow writes to all other protected registers defined in the specification. The write allow register is only writeable in M3 privilege mode.