The Stellaris® family of devices map Flash starting at address zero in the M3 memory space. The Concerto™ series instead have boot ROM mapped to this location. Again, please note that address zero in the boot ROM contains the NVIC, or the nested vectored interrupt controller. The boot ROM performs a number of operations and then transfers control to the user application. The user application can then setup the NVIC and remap it to dedicated RAM. The on-chip ROM of the device is 64 kB, and on top of the M3 boot loader code, the M3 ROM contains some mathematical tables. The IPC, or interprocessor communication code, also resides in this ROM memory. M3 boot ROM will not include a Flash API. The Flash technology is new on this device, so API will not be added to the ROM. Nothing that is used specifically for Ethernet stack or USB is in this ROM either. However, the boot ROM does include AES cryptography tables, which are identical to the Stellaris table. Only the M3 core can access its ROM block; it cannot be accessed from either the µDMA nor from the C28x core.