The exception model of the M3 is an interrupt service. The M3 is based on an exception model for handling interrupt, synchronous faults, and SVC exceptions. When an interrupt is serviced, the new stack pointer points to the IRQ top of the stack. The pre-IRQ top of stack is where the old stack pointer was pointing originally. Context is automatically saved on the stack. The NVIC mapping at address zero is in the boot ROM. After the boot ROM passes control to the main application, the NVIC can be initialized and remapped to RAM. Using a dedicated M3 RAM block for the NVIC is recommended to reduce system latency. On Concerto, other than the normal interrupts hooked to the NVIC, certain error conditions trigger exceptions. These include clock fail conditions detected, an external GPIO input signal has requested an NMI (similar to what happens on the Stellaris family of devices), an error condition is generated on the C28x side in vector fetch, or the C28 timed out and issued a reset to the C28 CPU. There is also a bus fault, which is generated for memory access errors and RAM and Flash uncorrectable data errors.