The M3 processor supports interrupts and system exceptions through the NVIC, or the nested vectored interrupt controller. The processor and the NVIC prioritize and handle all the exceptions in this controller. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions, except for reset. The NVIC registers control interrupt handling. There are ten exception types and all exceptions have a configurable priority except reset, hard fault, and NMI which are granted with the highest priority. A lower priority value indicates a higher priority, and by default, all exceptions with a configurable priority have a priority of zero. Interrupt service is automatically handled by the NVIC. When an interrupt is serviced, the initial state is automatically saved at the interrupt entry and restored at the end. The vector table entry is automatically read, as well. The NVIC supports nested interrupts and preemption, which makes threading and scheduling services very flexible and perfect for real-time operations. Full access to the NVIC controller is restricted to all but the privileged mode. The host subsystems support both level sensitive and edge triggered interrupts, but please note that a user has to clear the interrupt source at the beginning of the interrupt handler.