The Cortex™-M3 prime cell is a thirty two channel DMA controller, which off loads the heavy lifting from the processor core. Peripheral support relies on the ability to move data in and out of the ports. The µDMA controller can perform transfers between memory and peripherals. This has a dedicated channel for each supported on-chip module, meaning one channel for receive and another for transmit path for bi-directional peripherals. The µDMA controller uses an area of system memory to store a set of channel control structures in a table. This control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024 byte boundary. The control table may be one for primary or two for alternate entries for each µDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and a transfer mode. Multiple transfer modes are supported to cover all transfer scenarios from memory to memory, memory to peripheral, or peripheral to memory. There is a basic mode for very simple transfer scenarios where the µDMA controller simply performs transfers, as long as there are more items to transfer and a transfer request is present. There is also ping-pong mode which is for continuous data flow to and from peripherals. In this instance, the transfer uses two control structures, the primary and the alternate control structure. A transfer has started using the primary control structure. When the transfer using the primary control structure is complete, the µDMA controller reads the alternate control structure for that channel to continue the transfer. Once complete, the transfer switches back to the primary structure and the process starts over again. Another transfer mode is the scatter-gather, a programmable list of arbitrary transfers initiated from a single request. This is used when data must be transferred to or from varied locations in memory instead of in a contiguous location in the memory buffer. The µDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the µDMA controller. Each channel has a priority level bit to provide two levels of priority—a default priority and a high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all of the high priority channels. On Stellaris® devices, the M core has a higher priority than the µDMA accesses. On Concerto™ devices, access is allocated based on a round robin scheme. The difference in latencies may be a problem if the same memory is shared from µDMA and the M3 CPU, but this can be overcome by using dedicated C28x memories for time critical Cortex code or M3 code.